On Verifying the Correctness of Retimed Circuits

our verification program is especially customized to focus on how to trim down the search space, it does not use the guidance popularly adopted in a sequential ATPG program to find a test quickly if the two circuits are not equivalent. Hence, our program should be integrated with an original sequential ATPG program as a dual-program to handle different situations. For example, our verification program can verify the correctness of the retimed circuit s344 in 4.1 seconds, while stg3 (a sequential ATPG) cannot reached the conclusion that the miter's outputs are all untestable, (which is only the necessary condition) after searching for 10 hours. But on the other hand, we found a distinguishing sequence for s5378 and its retimed circuit in less than two minutes using stg3. For this case, our verification program would take much longer time to find a distinguishing sequence. Note that, a test sequence means these two circuits are neither 3-valued equivalent nor delayed equivalent, because no matter how many prefix input patterns have been applied to both circuits, this test sequence can still produce output combination (0, 1) or (1, 0).